As the dimensions of complimentary metal oxide semiconductor (CMOS) technology scale down, the capacitance in memory cells also scales, causing an increased sensitivity to upset by charged particles. Upsets from such particles are known as soft errors. Conventionally, to deal with this problem, parity bits are generated and stored as additional cells. This requires the generation and checking of the parity bits and in addition, consumes area and power.
FIG. 1 depicts a conventional register file 100 employing level sensitive scan design (LSSD) testing. Conventional file 100 includes a-clock and b-clock input ports 102, 104. Also included are scan-in true and complimentary ports 106, 108, and scan-out true and complimentary ports 110, 112.
The register file 100 includes a plurality of register file cells 114. In the example depicted in FIG. 1, these are arranged as n+1 rows numbered 0-n, and m+1 columns, numbered 0-m. Thus, the particular register file 100 contains n+1 entries having m+1 bits per word. Each cell has a-clock, b-clock, scan-in true, scan-in complimentary, scan-out true, and scan-out complimentary ports 116 through 126.
The particular example shown in FIG. 1 includes four write word lines numbered WWL0-WWL3, four read word lines numbered RWL0-RWL3, four write bit lines numbered WBL0-WBL3, and four read bit lines numbered RBL0-RBL3. Each register file cell 114 also includes appropriate ports for interconnection with the write and read word lines and write and read bit lines. Write decoders 128 and read decoders 130 are provided in a conventional manner.
Persons of skill in the art are familiar with the operation of conventional register files as shown in FIG. 1. For example, such register files are discussed in the book Principles of CMOS VLSI Design: A Systems Perspective, Second Edition, Neil H. E. Weste and Kameron Eshraghian, Addison & Wesley, Redding, 1993, at pages 580-582. Details of LSSD are also shown in the Weste and Eshraghian reference, at pages 489-493. During LSSD scan testing, the register file cells can be made scan-able and chained together, as described in U.S. Pat. No. 5,481,495 of Henkels et al., entitled “Cells And Read-Circuits For High-Performance Register Files.” The b-clock and a-clock are alternatively pulsed and the data is serially loaded into each register file cell through the scan-in port.
A bit line OR circuit 132 is also included, as in known in the art.
In U.S. Pat. No. 4,954,988 of Robb, entitled “Memory Device Wherein a Shadow Register Corresponds to Each Memory Cell,” a data storage device includes two registers associated with each cell of the memory. The first register forms a read/write memory register, and the second register forms a write-only shadow register connected to the memory register. During normal operations, each memory register operates as an independent random access memory (RAM) cell and each shadow register operates as an independent write-only RAM cell. When data is written to a shadow register, a flag bit is set. Subsequently, a validity check may be performed to verify the data. If the data does not verify, a clear line may be used to clear the flag bits. If the data verifies, the data in each shadow register with a flag bit set can be loaded into its corresponding memory register in a gang loading operation. If a shadow register flag bit is not set, the data in its corresponding memory register is not changed during gang loading. This technique does not address the need to verify the data at the time of the READ operation. In the techniques of the Robb reference, data in the shadow register could become corrupted by a soft error after being verified or after being written into the main storage latch.
It would be desirable to overcome the limitations in prior art approaches exemplified in FIG. 1.